Google has announced two new tensor processing unit (TPU) systems, aimed at increasing the memory available for massive agentic workloads and secure and confidential compute.

TPU 8i Max and TPU 8tx are the latest systems in Google’s eighth-generation TPU family. It announced the first chips in this generation, the training-focused TPU 8t and inference-focused TPU 8i, in April at its annual Google Cloud Next conference.

TPU 8tx is intended for use by governments or regulated enterprises looking to fine-tune AI models using private data or run frontier models alongside proprietary systems and information.

It shares the same base as TPU 8t, with 216 gigabytes of high-bandwidth memory (HBM) and 12.6 petaflops of FP4 compute, paired with AMD EPYC CPU hosts that enforce hardware-level PCIe link encryption, cryptographic attestation and secure memory enclaves.

Together, Google said, these ensure TPU 8tx runs a completely isolated environment in which organisations can run AI models without risk of them being compromised.

Google said TPU 8i Max is intended to address the “memory wall” that occurs when multiple AI agents are run in parallel on long-horizon tasks such as refactoring an entire codebase.

While built on the same hardware platform as TPU 8i, it is equipped with 384 gigabytes of HMB – 33 per cent more than TPU 8i – and 17.2 terabits per second of HBM bandwidth.

Google added that TPU 8i Max can scale compute and memory simultaneously, with twice the flops and SRAM, for “unprecedented agent density” before hitting the memory wall.

Amin Vahdat, senior vice president and chief technologist for AI and infrastructure at Google, said: “Instead of waiting years for a traditional semiconductor cycle, we keep innovating quickly, adapting directly to how workloads are evolving in real time.”

Alongside the hardware advancements, Google also announced a new commitment to making TPU development more open and improving TPU performance at the software level.

Last month, Google open-sourced TorchTPU. This is a PyTorch backend for Google’s TPUs, which allows developers to write AI code using the most popular deep learning frameworks and libraries on TPUs with few changes needed.

Alongside this Google has open-sourced TPU Sync, its model-state layer for TPU clusters, to allow organisations to control their chip HBM, shared storage, DRAM and networking to decrease latency and eliminate memory bottlenecks.

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